University of Pennsylvania · CIS 5710
Pipelined RV32IM Processor with AXI4-Lite Memory
A publication-safe processor repository centered on a final F/G/D/X/M/W pipeline. The added G stage handles instruction-memory response latency from the AXI4-Lite-style instruction interface, making front-end flow control and pipeline correctness the main engineering challenge.
SystemVerilogRV32IMAXI4-LiteCocotbVerilatorYosys/nextpnr
Six-stage RV32IM pipeline
F/G/D/X/M/W with an added instruction-response stage for AXI4-Lite-style fetch latency.
AXI4-Lite
F
Fetch
stage 1
G
Response
stage 2
D
Decode
stage 3
X
Execute
stage 4
M
Memory
stage 5
W
Writeback
stage 6
Forwarding + load-use stalls
Branch/jump flush
64 / 64 verification artifact
Overview
Project Strengths
- Six-stage F/G/D/X/M/W pipeline rather than a simplified five-stage CPU.
- AXI4-Lite-style instruction fetch with valid/ready flow control and instruction-response backpressure.
- Forwarding, load-use stalls, branch/jump flush, and divider dependency handling.
- Simulation and implementation evidence through Cocotb, Verilator, Yosys, nextpnr, and Lattice ECP5-oriented reports.
My Contribution
- Implemented AXI-Lite handshakes/backpressure, pipeline control, branch flushing, and load/store transaction handling.
- Debugged timing and trace failures with Cocotb/Verilator verification.
- Brought the design through an FPGA-oriented implementation flow using Yosys and nextpnr report artifacts.
System / Architecture
Architecture
- 01F issues instruction read requests and tracks fetch PC.
- 02G holds the returned instruction response before decode.
- 03D decodes, reads registers, and detects dependencies.
- 04X executes ALU/control work and resolves branches/jumps.
- 05M handles data-memory response and result selection.
- 06W commits writeback and trace-visible completion.
Implementation
Implementation
- Implemented processor-side AXI4-Lite-style manager logic for instruction and data memory.
- Coordinated stalls, flushes, and instruction-response readiness when memory responses arrive during pipeline backpressure.
- Integrated an 8-stage unsigned divider for RV32M divide/remainder operations with metadata tracking and special-case handling.
- Retained a self-contained RTL subset while excluding course-provided memory models, wrappers, and autograder infrastructure.
Six-stage RV32IM pipeline
F/G/D/X/M/W with an added instruction-response stage for AXI4-Lite-style fetch latency.
AXI4-Lite
F
Fetch
stage 1
G
Response
stage 2
D
Decode
stage 3
X
Execute
stage 4
M
Memory
stage 5
W
Writeback
stage 6
Forwarding + load-use stalls
Branch/jump flush
64 / 64 verification artifact
Results / Validation
- Functional verification result artifact reports 64 / 64.
- Final FPGA implementation summary reports 20.55 MHz Fmax against a 20.16 MHz target.
- Public repository makes no CPI, IPC, benchmark, power, or physical demo claims.
Challenges / Decisions
- AXI instruction-memory latency required the additional G stage and careful PC/instruction pairing.
- Branch redirects had to flush younger work that could be in fetch, instruction response, or decode.
- Load-use and divider dependencies required stalls without duplicating or losing memory responses.